Anza CEO Brennan Watt reported on August 7 that Solana's testnet had run eight consecutive hours of 350-millisecond slots, the first extended stability result under SIMD-0525, which governs the network's four-phase reduction of slot time toward a 200ms target.

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The first feature gate under SIMD-0525 activated on testnet on August 5, dropping the slot interval from 400ms to 350ms. Eight hours of continuous operation at the reduced setting, without elevated block skip rates, is the practical stability criterion the community attached to progression: each of the three remaining phase gates cannot proceed until the previous step proves it can hold.

SIMD-0525: Four Steps From 400ms to 200ms Slot Time

SIMD-0525, authored by Watt, structures the reduction as four sequential 50ms decrements: 400ms to 350ms, then 300ms, 250ms, and finally 200ms. Each step works through Solana's feature gate mechanism: a supermajority of stake-weighted validators must vote in favor before the gate activates, followed by a one-epoch delay of roughly two to three days before the new timing takes effect.

The proposal leaves ticks per slot, leader slot span, and slots per epoch unchanged. The change is classified as breaking: validators must run a client version that supports the new slot interval, or they default to voting against the feature gate.

Current testnet slot time
350ms
-12.5%vs 400ms baseline
Final target slot time
200ms
Phases remaining
3 of 4

Agave v4.2 and the August 17 Mainnet Window

The 400ms to 350ms step is scheduled to reach mainnet with Agave v4.2, which Anza targets for the week of August 17. That release bundles the slot time reduction with two other changes: block compute limits rising from 60M to 100M compute units, and maximum transaction size expanding from 1,232 to 4,096 bytes.

Mainnet activation follows the same supermajority-plus-one-epoch sequence used on testnet. Validators running Agave v4.2 can vote in favor; nodes on older clients cannot handle the new timing and oppose activation by default. The one-epoch buffer gives operators time to confirm stable behavior before the network commits to the change.

Slot Speed, Confirmation Time, and Censorship Resistance

A shorter slot compresses the window during which a block leader holds exclusive control over which transactions get included. Solana's official upgrade documentation frames this as a censorship-resistance benefit alongside throughput improvements, since a narrower leader window reduces the opportunity for selective transaction exclusion.

Mainnet compute blocks averaged about 29% utilization between August 1 and 6, per Solana Compass network data, with the network handling roughly 1,441 user transactions per second at the current 400ms slot interval.

The slot time work runs in parallel with Alpenglow, whose readiness components shipped with Agave v4.1 in June. Alpenglow targets finality in the 100-150ms range by optimizing the confirmation layer rather than block production cadence. The two initiatives address different parts of the latency stack.

Three more phase gates remain after mainnet adopts the 350ms step. Each depends on the previous step holding acceptable skip rates before the next feature gate vote can proceed.